1. Field of the Invention
The present invention relates to a method of fabricating an isolation shallow trench, and more particularly, to a method of fabricating a single side isolation shallow trench in a deep trench.
2. Description of the Prior Art
Along with the development of miniaturization of various electronic products, the design of the dynamic random access memory (DRAM) elements has to match the requirement of high integration and high density. DRAMs with trench capacitor structures have become one of the main structures of high-integrated DRAM products used in industry. This kind of DRAM contains trench capacitors fabricated inside deep trenches that are formed in a semiconductor substrate by an etching process so as to effectively reduce a size of the memory cell and utilize space of chips well. Furthermore, because the integration of the DRAM elements is becoming higher than ever, the distance between the adjacent memory cells is becoming smaller than what is available on the market. Recently, in order to prevent the defects such as electric leakage in the DRAM elements, a single side buried strap (SSBS) is designed to be formed on the trench capacitor of each memory cell and electrically connected to a source/drain of the corresponding transistor. The method of the above-mentioned structure can be practiced by forming a single side isolation shallow trench on the trench capacitor opposite to the SSBS so as to isolate the buried strap or trench capacitor from the adjacent memory cells.
FIG. 1 through FIG. 6 are schematic diagrams illustrating the method of fabricating a single side isolation shallow trench of the prior art. With reference to FIG. 1, a semiconductor device 10 including a substrate 12 is provided, and the surface of the semiconductor device 10 includes a pad layer 20 and a deep trench 14 defined in the substrate 12. The deep trench 14 includes a lower portion 16 and an upper portion 18. An oxide layer 24 is disposed on the inner surface of the sidewall of the lower portion 16 of the deep trench 14, and the inside of the deep trench 14 is filled with a conductive layer 22. A nitride layer 26 is disposed on the surface of the conductive layer 22.
Next, as shown in FIG. 2, a liner layer 27 is formed on a surface of the substrate 12, and the liner layer 27 covers the top surface of the pad layer 20, the inner side wall of the deep trench 14 and an exposed surface of the nitride layer 26. The liner layer 27 can be an amorphous silicon layer or a poly-silicon layer. With reference to FIG. 3, an implant process 28 is performed to implant boron fluoride ions into the liner layer 27 with an angle α so that portions of the liner layer 27 forms a doped layer 30, as shown in FIG. 4. It is to be noted that the implant process 28 is to implant the boron fluoride ions into the liner layer 27 with a predetermined angle α, so that a portion of the liner layer 27 will not become the doped layer 30 due to said portion of the liner layer 27 being shielded by the sidewall of the deep trench 14. Sequentially, a wet etching process is performed with an etchant including ammonia to remove said portion of the liner layer 27 not becoming the doped layer 30. Therefore, an opening 32 exposing a portion of the nitride layer 26 is formed on the surface of the nitride layer 26.
Next, with reference to FIG. 5, an oxidation process is performed to make the doped layer 30 become an oxidation mask layer 34. As shown in FIG. 6, the oxidation mask layer 34 is taken as an etching mask, and an etching process is performed to the substrate 12 to remove portions of the nitride layer 26 and the conductive layer 22 not covered by the oxidation mask layer 34 so as to form a shallow trench 36 in the deep trench 14. Sequentially, an isolation shallow trench can be formed in the shallow trench 36 so as to isolate the memory cell of the deep trench 14 from the other elements on the left side of the memory cell.
As mentioned above, a size of the isolation shallow trench in the deep trench 14 is determined by the angle α of the implant process 28. The size of the isolation shallow trench will become larger as the angle α is larger. When the element integration is becoming high and the sizes of each memory cell and the deep trench 14 become small, the angle α also has to make the necessary adjustment so as to reduce the size of the isolation shallow trench accordingly. However, the implant process 28 with a small angle α has a small process window, whose process difficulty is correspondingly high. Especially when the process level advances to 90 nanometers or even under 60 nanometers, the difficulty of the above-mentioned process of the prior art is also greatly increased to affect the cost and process yield.
On the other hand, according to the process of fabricating isolation shallow trench of the prior art, the steps of the wet etching process and the oxidation process have to be performed sequentially after the implant process 28 so that the oxidation mask layer 34 utilized to fabricate the isolation shallow trench can be formed on the surface of the nitride layer 26. Accordingly, the prior-art processes are too complicated to increase the process efficiency.
Therefore, how to fabricate an isolation shallow trench having a good structure in the deep trench by a simple process with improved process window and process yield is still required for the industry.